Clifford Wolf 6aa792c864 Replaced more old SigChunk programming patterns

2014-07-24 23:10:58 +02:00

..

ast

Replaced more old SigChunk programming patterns

2014-07-24 23:10:58 +02:00

ilang

Added "make PRETTY=1"

2014-07-24 17:15:01 +02:00

liberty

SigSpec refactoring: using the accessor functions everywhere

2014-07-22 20:39:37 +02:00

verific

Various fixes in Verific frontend for new RTLIL API

2014-07-23 21:35:01 +02:00

verilog

Added "make PRETTY=1"

2014-07-24 17:15:01 +02:00

vhdl2verilog

Added passing of various options to vhdl2verilog

2014-07-12 10:02:39 +02:00