Charlotte 7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse ...

See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.

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..

appendix

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APPNOTE_011_Design_Investigation

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CHAPTER_Prog

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bib.rst

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CHAPTER_Approach.rst

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CHAPTER_Basics.rst

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CHAPTER_CellLib.rst

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CHAPTER_Eval.rst

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CHAPTER_Intro.rst

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CHAPTER_Memorymap.rst

docs: reflow memory map

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CHAPTER_Optimize.rst

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CHAPTER_Overview.rst

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CHAPTER_Prog.rst

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CHAPTER_Techmap.rst

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CHAPTER_Verilog.rst

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cmd_ref.rst

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conf.py

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index.rst

Initial version of memory mapping doc

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literature.bib

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requirements.txt

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