clairexen 802671b22e Merge pull request #2244 from antmicro/logic ...

Add logic type support to parameters

2020-07-09 18:39:30 +02:00

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aiger

tests: aiger test for wire->start_offset != 0

2020-05-02 10:00:32 -07:00

arch

gowin: Use dfflegalize.

2020-07-06 12:27:46 +02:00

asicworld

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bram

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errors

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fsm

tests: fsm to use a randomly-generated seed

2020-04-24 14:31:33 -07:00

hana

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liberty

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lut

Forgot to commit

2019-07-16 12:44:26 -07:00

memfile

Added 'set -e' into tests/memfile/run-test.sh

2020-02-06 10:45:40 -03:00

memories

memory_dff: Fix checking of feedback mux input when more than one mux

2019-07-02 13:35:50 +01:00

opt

opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.

2020-07-05 06:31:58 +02:00

opt_share

Support various binary operators in opt_share

2019-08-04 19:06:38 +02:00

proc

proc_clean: fix order of switch insertion.

2019-08-19 16:44:23 +00:00

realmath

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rpc

rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors

2020-03-06 15:29:01 +01:00

sat

Merge pull request #1638 from YosysHQ/eddie/fix1631

2020-02-05 19:31:18 +01:00

select

Merge pull request #1949 from YosysHQ/eddie/select_blackbox

2020-04-22 15:35:05 -07:00

share

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simple

Expand tests/simple/constmuldivmod.v

2020-05-28 22:59:04 +02:00

simple_abc9

abc9: test to use box file instead of auto

2020-05-14 10:33:56 -07:00

smv

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sva

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svinterfaces

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svtypes

static cast: add tests

2020-06-19 17:40:38 -07:00

techmap

clk2fflogic: Consistently treat async control signals as negative hold.

2020-07-09 18:12:47 +02:00

tools

autotest.sh to define _AUTOTB when test_autotb

2019-06-28 14:56:22 -07:00

unit

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various

Add logic param and integer bad syntax tests

2020-07-06 09:18:48 +02:00

verilog

Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings

2020-06-03 08:37:07 -07:00

vloghtb

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