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82965d60f53c817fea303abf8d6887ced8c8420e
YosysHQ.yosys
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tests
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svinterfaces
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Ruben Undheim
397dfccb30
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
..
run-test.sh
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
runone.sh
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface1_ref.v
…
svinterface1_tb.v
…
svinterface1.sv
…
svinterface_at_top_ref.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top_tb_wrapper.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top_tb.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top_wrapper.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top.sv
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
