Tim 'mithro' Ansell d6bdefd2e9 Improving vpr output support. ...

* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.

2018-04-18 16:55:12 -07:00

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tests

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.gitignore

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arith_map.v

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brams_bb.v

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brams_init.py

Squelch trailing whitespace, including meta-whitespace

2018-03-11 16:03:41 +01:00

brams_map.v

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brams.txt

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cells_map.v

Improving vpr output support.

2018-04-18 16:55:12 -07:00

cells_sim.v

Add Xilinx RAM64X1D and RAM128X1D simulation models

2018-03-07 17:31:48 +01:00

cells_xtra.sh

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cells_xtra.v

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drams_map.v

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drams.txt

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lut2lut.v

Add techlibs/xilinx/lut2lut.v

2017-07-10 12:09:05 +02:00

Makefile.inc

Add Xilinx RAM64X1D and RAM128X1D simulation models

2018-03-07 17:31:48 +01:00

synth_xilinx.cc

Improving vpr output support.

2018-04-18 16:55:12 -07:00