Claire Xenia Wolf 3fb32540ea Add propagated clock signals into btor info file

2022-05-04 08:10:18 +02:00

..

aiger

Add -no-startoffset option to write_aiger

2022-03-25 08:44:45 +01:00

blif

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

btor

Add propagated clock signals into btor info file

2022-05-04 08:10:18 +02:00

cxxrtl

Add $bmux and $demux cells.

2022-01-28 23:34:41 +01:00

edif

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

firrtl

Add $bmux and $demux cells.

2022-01-28 23:34:41 +01:00

intersynth

Intersynth URL

2021-06-09 12:42:52 +02:00

jny

pass jny: flipped the defaults for the inclusion of various bits of metadata

2022-04-08 08:05:15 +02:00

json

Merge pull request #3210 from rqou/json-signed

2022-03-07 09:41:25 +01:00

protobuf

Fix protobuf backend build dependencies

2021-09-17 13:36:39 +10:00

rtlil

rtlil: Dump empty connections when whole module is selected.

2021-12-12 01:22:06 +01:00

simplec

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

smt2

smt2: Make write port array stores conditional on nonzero write mask

2022-04-20 17:49:48 +02:00

smv

Add $bmux and $demux cells.

2022-01-28 23:34:41 +01:00

spice

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

table

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

verilog

verilog backend: Emit a wire for ports as well.

2022-01-31 01:08:41 +01:00