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YosysHQ.yosys/frontends/ast
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Jannis Harder 79e05a195d verilog: Bufnorm cell backend and frontend support 
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
2025-09-17 14:01:09 +02:00
..
ast_binding.cc
Generate an RTLIL representation of bind constructs
2021-08-13 17:11:35 -06:00
ast_binding.h
Generate an RTLIL representation of bind constructs
2021-08-13 17:11:35 -06:00
ast.cc
Remove .c_str() calls from parameters to log_header()
2025-09-16 23:00:42 +00:00
ast.h
Make AstNode::input_error use C++ stringf machinery
2025-09-12 06:01:32 +00:00
dpicall.cc
Remove .c_str() calls from log()/log_error()
2025-09-11 20:59:37 +00:00
genrtlil.cc
Remove some unnecessary .c_str() calls to the result of unescape_id()
2025-09-16 23:12:14 +00:00
Makefile.inc
Generate an RTLIL representation of bind constructs
2021-08-13 17:11:35 -06:00
simplify.cc
verilog: Bufnorm cell backend and frontend support
2025-09-17 14:01:09 +02:00