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YosysHQ.yosys/tests/verilog/unmatched_else.ys
Zachary Snow 1ec5994100 verilog: fix handling of nested ifdef directives
- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
2021-03-01 12:28:33 -05:00

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logger -expect error "Found `else outside of macro conditional branch!" 1
read_verilog <<EOT
module top;
`else
endmodule
EOT