github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-24 11:32:04 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/techlibs/anlogic
History
gatecat cae905f551 Blackbox all whiteboxes after synthesis 
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
..
anlogic_eqn.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
anlogic_fixcarry.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
arith_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cells_map.v
anlogic: Fix FF mapping.
2020-07-17 14:03:21 +02:00
cells_sim.v
anlogic: Use dfflegalize.
2020-07-14 05:02:50 +02:00
eagle_bb.v
Revert "Leave only real black box cells"
2018-12-17 23:20:40 +08:00
lutram_init_16x4.vh
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
lutrams_map.v
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
lutrams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
Makefile.inc
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
synth_anlogic.cc
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00