Eddie Hung 88bddb37c9 verilog: handle empty generate statement by removing gen_stmt_or_null... ...

... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.

2020-05-25 07:36:53 -07:00

..

.gitignore

Add "make coverage"

2018-08-27 14:22:21 +02:00

const2ast.cc

Replacing log_error for log_file_error due consistency

2020-03-31 12:01:29 -06:00

Makefile.inc

Add one mode dependency

2020-03-19 16:53:40 +01:00

preproc.cc

Add support for SystemVerilog-style `define to Verilog frontend

2020-03-27 16:08:26 +00:00

preproc.h

Add support for SystemVerilog-style `define to Verilog frontend

2020-03-27 16:08:26 +00:00

verilog_frontend.cc

frontend: cleanup to use more ID::*, more dict<> instead of map<>

2020-05-04 10:48:37 -07:00

verilog_frontend.h

frontend: cleanup to use more ID::*, more dict<> instead of map<>

2020-05-04 10:48:37 -07:00

verilog_lexer.l

Error duplicate declarations of a typedef name in the same scope.

2020-03-24 14:35:21 +00:00

verilog_parser.y

verilog: handle empty generate statement by removing gen_stmt_or_null...

2020-05-25 07:36:53 -07:00