Miodrag Milanovic 27c5bafc95 Proper example code

2022-03-14 15:39:11 +01:00

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aiger

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arch

intel_alm: M10K write-enable is negative-true

2022-03-09 20:18:06 +00:00

asicworld

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bind

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blif

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bram

Fix the tests we just broke

2021-12-10 00:22:37 +01:00

errors

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fsm

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hana

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liberty

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lut

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memfile

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memories

Fix the tests we just broke

2021-12-10 00:22:37 +01:00

opt

opt_reduce: Add $bmux and $demux optimization patterns.

2022-01-30 03:37:52 +01:00

opt_share

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proc

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realmath

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rpc

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sat

Proper example code

2022-03-14 15:39:11 +01:00

select

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share

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sim

test dlatchsr and adlatch

2022-02-16 13:58:51 +01:00

simple

fix iverilog compatibility for new case expr tests

2022-01-03 12:11:41 -07:00

simple_abc9

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smv

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sva

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svinterfaces

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svtypes

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techmap

Fix the tests we just broke

2021-12-10 00:22:37 +01:00

tools

Fixes in vcdcd.pl for newer Perl versions

2021-10-19 10:56:43 +02:00

unit

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various

fix handling of escaped chars in json backend and frontend

2022-02-18 17:13:09 +01:00

verilog

verilog: support for time scale delay values

2022-02-14 15:58:31 +01:00

vloghtb

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gen-tests-makefile.sh

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