Claire Xenia Wolf 8aee80040d Add default assignments to SB_LUT4 ...

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>

2021-04-20 12:46:21 +02:00

..

aiger

switch argument order to work with macOS getopt

2020-09-23 12:48:26 +02:00

arch

Add default assignments to SB_LUT4

2021-04-20 12:46:21 +02:00

asicworld

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00

bram

tests/bram: Do not generate write address collisions.

2021-03-08 16:53:03 +01:00

errors

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

fsm

tests: fsm to use a randomly-generated seed

2020-04-24 14:31:33 -07:00

hana

Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.

2016-09-22 11:49:29 -06:00

liberty

dfflibmap: Refactor to use dfflegalize internally.

2020-07-09 18:51:03 +02:00

lut

Forgot to commit

2019-07-16 12:44:26 -07:00

memfile

Added 'set -e' into tests/memfile/run-test.sh

2020-02-06 10:45:40 -03:00

memories

tests: Parallelize

2020-09-21 15:07:02 +02:00

opt

opt_clean: Remove init attribute bits together with removed DFFs.

2021-03-15 17:16:53 +01:00

opt_share

tests: Parallelize

2020-09-21 15:07:02 +02:00

proc

proc_arst: Add special-casing of clock signal in conditionals.

2021-03-15 17:17:29 +01:00

realmath

Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.

2016-09-22 11:49:29 -06:00

rpc

rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors

2020-03-06 15:29:01 +01:00

sat

assertpmux: Fix crash on unused $pmux output.

2021-02-22 23:30:28 +01:00

select

Merge pull request #1949 from YosysHQ/eddie/select_blackbox

2020-04-22 15:35:05 -07:00

share

Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.

2016-09-22 11:49:29 -06:00

simple

verilog: fix buf/not primitives with multiple outputs

2021-03-17 11:44:03 -04:00

simple_abc9

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

smv

Progress in SMV back-end

2015-06-19 14:08:46 +02:00

sva

Fix "verific -extnets" for more complex situations

2019-03-26 14:17:46 +01:00

svinterfaces

Fix typo in tests/svinterfaces/runone.sh

2019-05-03 14:40:51 +02:00

svtypes

verilog: check entire user type stack for type definition

2021-03-21 19:35:13 -04:00

techmap

Add tests for some common techmap files.

2021-02-24 01:07:34 +01:00

tools

memory_dff: Remove now-useless write port handling.

2021-03-08 20:16:29 +01:00

unit

Build hotfix in tests/unit/Makefile

2016-12-11 10:58:49 +01:00

various

abc9: uniquify blackboxes like whiteboxes (#2695)

2021-03-29 22:02:06 -07:00

verilog

preproc: test coverage for #2712

2021-03-30 12:23:18 -04:00

vloghtb

bugfix in blif front-end

2015-05-18 11:15:49 +02:00

gen-tests-makefile.sh

tests: Parallelize

2020-09-21 15:07:02 +02:00