Clifford Wolf 8b0f50792c Added techmap -extern

2014-07-27 21:31:18 +02:00

..

abc

Refactoring: Renamed RTLIL::Design::modules to modules_

2014-07-27 11:18:30 +02:00

cmds

Refactoring: Renamed RTLIL::Design::modules to modules_

2014-07-27 11:18:30 +02:00

fsm

Added log_cmd_error_expection

2014-07-27 12:05:50 +02:00

hierarchy

Refactoring: Renamed RTLIL::Design::modules to modules_

2014-07-27 11:18:30 +02:00

memory

Using new obj iterator API in a few places

2014-07-27 11:32:42 +02:00

opt

Added SigPool::check(bit)

2014-07-27 15:38:02 +02:00

proc

Using new obj iterator API in a few places

2014-07-27 11:32:42 +02:00

sat

Refactoring: Renamed RTLIL::Design::modules to modules_

2014-07-27 11:18:30 +02:00

techmap

Added techmap -extern

2014-07-27 21:31:18 +02:00