Marcelina Kościelnicka 0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. ...

This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.

2021-12-12 19:56:50 +01:00

..

Makefile.inc

initial import

2013-01-05 11:13:26 +01:00

verilog_backend.cc

Add clean_zerowidth pass, use it for Verilog output.

2021-12-12 19:56:50 +01:00