Clifford Wolf fcae92868d Fixed dumping of timing() { .. } block in libparse

2014-03-09 15:16:07 +01:00

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abc

Verbose reading of liberty and constr files in ABC pass

2014-03-09 15:15:38 +01:00

cmds

Added "design -push" and "design -pop"

2014-02-20 23:28:59 +01:00

fsm

Fixes in fsm detect/extract for better detection of non-fsm circuits

2013-12-06 12:53:20 +01:00

hierarchy

Implemented read_verilog -defer

2014-02-13 13:59:13 +01:00

memory

Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect

2014-02-08 19:13:19 +01:00

opt

Fixed undef handling in opt_reduce

2014-03-06 14:18:34 +01:00

proc

Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst

2014-02-21 23:34:45 +01:00

sat

Fixed bug in freduce command

2014-03-07 18:44:23 +01:00

techmap

Fixed dumping of timing() { .. } block in libparse

2014-03-09 15:16:07 +01:00