71 lines
995 B
Plaintext
71 lines
995 B
Plaintext
# LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7.
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# The corresponding mapping file is lutrams_xc5v_map.v
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# Single-port RAMs.
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ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
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cost 8;
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widthscale;
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option "ABITS" 5 {
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abits 5;
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widths 8 global;
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}
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option "ABITS" 6 {
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abits 6;
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widths 4 global;
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}
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init no_undef;
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prune_rom;
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port arsw "RW" {
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clock posedge;
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}
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}
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# Dual-port RAMs.
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ram distributed $__ANALOGDEVICES_LUTRAM_DP_ {
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cost 8;
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widthscale;
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option "ABITS" 5 {
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abits 5;
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widths 4 global;
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}
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option "ABITS" 6 {
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abits 6;
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widths 2 global;
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}
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option "ABITS" 7 {
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abits 7;
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widths 1 global;
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}
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init no_undef;
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prune_rom;
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port arsw "RW" {
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clock posedge;
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}
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port ar "R" {
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}
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}
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# Simple dual port RAMs.
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ram distributed $__ANALOGDEVICES_LUTRAM_SDP_ {
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cost 8;
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widthscale 7;
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option "ABITS" 5 {
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abits 5;
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widths 6 global;
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}
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option "ABITS" 6 {
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abits 6;
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widths 3 global;
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}
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init no_undef;
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prune_rom;
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port sw "W" {
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clock posedge;
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}
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port ar "R" {
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}
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}
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