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mirror of synced 2026-02-21 15:07:30 +00:00
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YosysHQ.yosys/techlibs/lattice/cells_sim_xo2.v
Miodrag Milanovic e3c15f003e Create synth_lattice
2023-08-23 10:53:21 +02:00

10 lines
125 B
Verilog

`include "common_sim.vh"
`include "ccu2d_sim.vh"
`ifndef NO_INCLUDES
`include "cells_ff.vh"
`include "cells_io.vh"
`endif