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YosysHQ.yosys/tests/arch/common/tribuf.v
Miodrag Milanovic 9bd9db56c8 Unify verilog style
2019-10-18 12:50:24 +02:00

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Verilog

module tristate(en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule