17 lines
224 B
Plaintext
17 lines
224 B
Plaintext
read_verilog -sv <<EOF
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module top ();
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always_comb begin
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label1: cover(0);
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label2: cover(0);
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end
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endmodule
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EOF
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hierarchy -top top
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proc
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chformal -lower
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clean
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opt_merge
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select -assert-count 2 t:$cover
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