e7156c644d
genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration. Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.
27 lines
382 B
Plaintext
27 lines
382 B
Plaintext
read_verilog <<EOT
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module foo;
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genvar a;
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for (a = 0; a < 10; a++) begin : a
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end : a
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endmodule
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EOT
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read_verilog <<EOT
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module foo2;
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genvar a;
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for (a = 0; a < 10; a++) begin : a
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end
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endmodule
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EOT
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logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
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read_verilog <<EOT
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module foo3;
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genvar a;
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for (a = 0; a < 10; a++) begin : a
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end : b
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endmodule
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EOT
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