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Clifford Wolf 9087ece97c OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys

(see https://github.com/cliffordwolf/yosys/pull/28)

2014-03-11 14:52:37 +01:00

..

Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys

2014-03-11 14:24:24 +01:00

Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys

2014-03-11 14:24:24 +01:00

Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys

2014-03-11 14:24:24 +01:00

Implemented read_verilog -defer

2014-02-13 13:59:13 +01:00

Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect

2014-02-08 19:13:19 +01:00

Fixed undef handling in opt_reduce

2014-03-06 14:18:34 +01:00

Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst

2014-02-21 23:34:45 +01:00

Fixed bug in freduce command

2014-03-07 18:44:23 +01:00

OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys

2014-03-11 14:52:37 +01:00