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YosysHQ.yosys/techlibs/xilinx
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Eddie Hung 723815b384 Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-30 13:26:19 -07:00
..
tests
DSP48E1 sim model: add SIMD tests
2019-08-08 11:39:35 +01:00
.gitignore
…
abc_xc7_nowide.lut
Add _nowide variants of LUT libraries in -nowidelut flows
2019-06-26 10:23:29 -07:00
abc_xc7.box
Fix $__XILINX_MUXF78 box timing
2019-07-01 14:04:06 -07:00
abc_xc7.lut
Simplify comment
2019-06-17 19:14:41 -07:00
arith_map.v
Instead of MUXCY/XORCY use CARRY4 (with timing)
2019-05-21 16:19:45 -07:00
brams_init.py
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
cells_map.v
xilinx: Fix missing cell name underscore in cells_map.v
2019-07-25 08:19:07 +01:00
cells_sim.v
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-30 09:50:20 -07:00
cells_xtra.py
move attributes to wires
2019-08-13 19:36:59 +00:00
cells_xtra.v
Merge branch 'master' into xc7dsp
2019-08-30 13:57:15 +01:00
dsp_map.v
Remove signed from ports in +/xilinx/dsp_map.v
2019-08-08 16:33:20 -07:00
ff_map.v
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
2019-07-11 21:13:12 +02:00
lut_map.v
Really permute Xilinx LUT mappings as default LUT6.I5:A6
2019-06-18 11:48:48 -07:00
lutrams_map.v
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
lutrams.txt
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
Makefile.inc
Merge branch 'master' into xc7dsp
2019-08-30 13:57:15 +01:00
mux_map.v
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
synth_xilinx.cc
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-30 13:26:19 -07:00
xc6s_brams_bb.v
move attributes to wires
2019-08-13 19:36:59 +00:00
xc6s_brams_map.v
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
xc6s_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_brams_bb.v
move attributes to wires
2019-08-13 19:36:59 +00:00
xc7_brams_map.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00