This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-04-24 19:40:49 +00:00
Code
Issues
Releases
Wiki
Activity
Files
90b016716b363977cf3dfc84d9502913469296ec
YosysHQ.yosys
/
frontends
/
verilog
History
Clifford Wolf
23cf23418c
Fixed handling of boolean attributes (frontends)
2013-10-24 11:20:13 +02:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
const2ast.cc
Major redesign of expr width/sign detecion (verilog/ast frontend)
2013-07-09 14:31:57 +02:00
lexer.l
fixed Verilog parser filename and line numbering issue with include files
2013-08-21 09:20:59 +02:00
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
parser.y
Fixed handling of boolean attributes (frontends)
2013-10-24 11:20:13 +02:00
preproc.cc
Added support for include directories with the new '-I' argument of the
2013-08-20 15:48:16 +02:00
verilog_frontend.cc
Added support for include directories with the new '-I' argument of the
2013-08-20 15:48:16 +02:00
verilog_frontend.h
Added support for include directories with the new '-I' argument of the
2013-08-20 15:48:16 +02:00