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914aa8a5d3c884df0eafbef87fdeb9c3594ebd5f
YosysHQ.yosys
/
techlibs
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gowin
History
Clifford Wolf
3db2ac4e00
Added hex constant support to write_verilog
2016-11-03 12:13:23 +01:00
..
cells_map.v
Added initial version of "synth_gowin"
2016-11-01 11:31:13 +01:00
cells_sim.v
Added initial version of "synth_gowin"
2016-11-01 11:31:13 +01:00
Makefile.inc
Added initial version of "synth_gowin"
2016-11-01 11:31:13 +01:00
synth_gowin.cc
Added hex constant support to write_verilog
2016-11-03 12:13:23 +01:00
