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915e7dde734094e21803f83e37f8827b8ff2fe32
YosysHQ.yosys
/
techlibs
/
xilinx
History
Eddie Hung
915e7dde73
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-14 12:57:56 -08:00
..
tests
…
.gitignore
…
abc9_map.v
Adding (* techmap_autopurge *) to FD* in abc9_map.v
2020-01-14 12:22:21 -08:00
abc9_model.v
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abc9_unmap.v
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abc9_xc7_nowide.lut
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abc9_xc7.box
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abc9_xc7.lut
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arith_map.v
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brams_init.py
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cells_map.v
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cells_sim.v
Add abc9_required to DSP48E1.{A,B,C,D,PCIN}
2020-01-10 17:12:31 -08:00
cells_xtra.py
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cells_xtra.v
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lut_map.v
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lutrams_map.v
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lutrams.txt
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Makefile.inc
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mux_map.v
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synth_xilinx.cc
Merge pull request
#1623
from YosysHQ/mmicko/edif_attr
2020-01-14 19:19:32 +01:00
xc3s_mult_map.v
…
xc3sda_dsp_map.v
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xc4v_dsp_map.v
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xc5v_dsp_map.v
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xc6s_brams_map.v
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xc6s_brams.txt
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xc6s_dsp_map.v
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xc6s_ff_map.v
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xc7_brams_map.v
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xc7_dsp_map.v
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xc7_ff_map.v
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xc7_xcu_brams.txt
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xcu_brams_map.v
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xcu_dsp_map.v
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xcup_urams_map.v
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xcup_urams.txt
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xilinx_dffopt.cc
…
