Eddie Hung 4f889b2f57 Merge pull request #1724 from YosysHQ/eddie/abc9_specify ...

abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries

2020-03-02 12:32:27 -08:00

..

achronix

Remove executable flag from files

2020-02-15 10:36:44 +01:00

anlogic

synth_*: call 'opt -fast' after 'techmap'

2020-02-05 18:39:01 -08:00

common

Create +/abc9_model.v for $__ABC9_{DELAY,FF_}

2020-02-27 10:17:29 -08:00

coolrunner2

coolrunner2: Attempt to give wires/cells more meaningful names

2020-03-02 01:40:57 -08:00

easic

Update doc that "-retime" calls abc with "-dff -D 1"

2019-12-30 13:28:29 -08:00

ecp5

synth_ecp5: use +/abc9_model.v

2020-02-27 10:17:29 -08:00

efinix

synth_*: call 'opt -fast' after 'techmap'

2020-02-05 18:39:01 -08:00

gowin

Removing cells_sim.v from bram techmap pass

2020-02-06 14:38:29 -06:00

greenpak4

synth_*: call 'opt -fast' after 'techmap'

2020-02-05 18:39:01 -08:00

ice40

ice40: add delays to SB_CARRY

2020-02-27 10:17:29 -08:00

intel

Add log_experimental() and experimental() API and "yosys -x"

2020-01-27 18:27:47 +01:00

sf2

synth_*: call 'opt -fast' after 'techmap'

2020-02-05 18:39:01 -08:00

xilinx

Remove RAMB{18,36}E1 from cells_xtra.py

2020-02-27 10:33:04 -08:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00