Claire Wolf 926a010b49 Merge pull request #1848 from YosysHQ/eddie/fix_dynslice ...

ast: simplify to fully populate dynamic slicing case transformation

2020-04-01 08:38:14 +02:00

..

aiger

tests/aiger: Add missing .gitignore

2020-02-15 19:52:21 +01:00

arch

fix argument order for macOS compatibility

2020-03-18 15:11:49 +01:00

asicworld

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00

bram

Added support for (single-clock) transparent memories to bram tests

2016-11-01 10:03:13 +01:00

errors

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

fsm

Speed up "make test" and related cleanups

2019-08-17 14:37:07 +02:00

hana

Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.

2016-09-22 11:49:29 -06:00

liberty

Liberty file parser now accepts superfluous ;

2019-03-27 15:16:19 +01:00

lut

Forgot to commit

2019-07-16 12:44:26 -07:00

memfile

Added 'set -e' into tests/memfile/run-test.sh

2020-02-06 10:45:40 -03:00

memories

memory_dff: Fix checking of feedback mux input when more than one mux

2019-07-02 13:35:50 +01:00

opt

opt_merge: speedup

2020-03-16 12:43:54 -07:00

opt_share

Support various binary operators in opt_share

2019-08-04 19:06:38 +02:00

proc

proc_clean: fix order of switch insertion.

2019-08-19 16:44:23 +00:00

realmath

Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.

2016-09-22 11:49:29 -06:00

rpc

rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors

2020-03-06 15:29:01 +01:00

sat

Merge pull request #1638 from YosysHQ/eddie/fix1631

2020-02-05 19:31:18 +01:00

select

Do not warn on empty selection with prefixed arg_memb.

2020-03-23 17:50:11 +00:00

share

Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.

2016-09-22 11:49:29 -06:00

simple

Add dynamic slicing Verilog testcase

2020-03-31 11:51:31 -07:00

simple_abc9

Update simple_abc9 tests

2020-02-27 10:17:29 -08:00

smv

Progress in SMV back-end

2015-06-19 14:08:46 +02:00

sva

Fix "verific -extnets" for more complex situations

2019-03-26 14:17:46 +01:00

svinterfaces

Fix typo in tests/svinterfaces/runone.sh

2019-05-03 14:40:51 +02:00

svtypes

Support module/package/interface/block scope for typedef names.

2020-03-23 20:07:22 +00:00

techmap

techmap: Fix cell names with _TECHMAP_REPLACE_.*

2020-03-23 11:17:07 +01:00

tools

autotest.sh to define _AUTOTB when test_autotb

2019-06-28 14:56:22 -07:00

unit

Build hotfix in tests/unit/Makefile

2016-12-11 10:58:49 +01:00

various

Add support for SystemVerilog-style `define to Verilog frontend

2020-03-27 16:08:26 +00:00

vloghtb

bugfix in blif front-end

2015-05-18 11:15:49 +02:00