1
0
mirror of synced 2026-02-09 10:01:03 +00:00
Files
YosysHQ.yosys/frontends
Jannis Harder 96f64f4788 verific: Fix conditions of SVAs with explicit clocks within procedures
For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
2022-05-03 14:13:08 +02:00
..
2020-10-19 13:40:57 +02:00
2021-10-01 21:18:33 -06:00