Jannis Harder 96f64f4788 verific: Fix conditions of SVAs with explicit clocks within procedures ...

For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.

2022-05-03 14:13:08 +02:00

..

.gitignore

Add simple VHDL+PSL example

2017-07-28 17:39:43 +02:00

basic00.sv

Improve SVA tests, add Makefile and scripts

2017-07-27 11:42:05 +02:00

basic01.sv

Squelch a little more trailing whitespace

2018-12-29 12:46:54 +01:00

basic02.sv

Improve SVA tests, add Makefile and scripts

2017-07-27 11:42:05 +02:00

basic03.sv

Improve SVA tests, add Makefile and scripts

2017-07-27 11:42:05 +02:00

basic04.sv

Improve SVA tests, add Makefile and scripts

2017-07-27 11:42:05 +02:00

basic04.vhd

Improve SVA tests, add Makefile and scripts

2017-07-27 11:42:05 +02:00

basic05.sv

Improve SVA tests, add Makefile and scripts

2017-07-27 11:42:05 +02:00

basic05.vhd

Improve SVA tests, add Makefile and scripts

2017-07-27 11:42:05 +02:00

counter.sv

Improve Verific SVA importer

2017-07-27 14:05:09 +02:00

extnets.sv

Fix "verific -extnets" for more complex situations

2019-03-26 14:17:46 +01:00

Makefile

Add simple VHDL+PSL example

2017-07-28 17:39:43 +02:00

nested_clk_else.sv

verific: Fix conditions of SVAs with explicit clocks within procedures

2022-05-03 14:13:08 +02:00

runtest.sh

Add support for SVA sequence concatenation ranges via verific

2018-02-18 16:35:06 +01:00

sva_not.sv

Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF

2018-02-15 15:26:37 +01:00

sva_range.sv

Major redesign of Verific SVA importer

2018-02-27 20:33:15 +01:00

sva_throughout.sv

Add support for SVA throughout via Verific

2018-02-21 13:09:47 +01:00