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97710ffad5d4750b538dac5f08b77dce37e3cda4
YosysHQ.yosys
/
techlibs
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common
History
Clifford Wolf
8406e7f7b6
Strictly zero-extend unsigned A-inputs of shift operations in techmap
2014-03-06 12:15:44 +01:00
..
blackbox.sed
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
Makefile.inc
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
pmux2mux.v
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
simcells.v
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
simlib.v
Added $slice and $concat cell types
2014-02-07 17:44:57 +01:00
stdcells.v
Strictly zero-extend unsigned A-inputs of shift operations in techmap
2014-03-06 12:15:44 +01:00