11 lines
198 B
Verilog
11 lines
198 B
Verilog
(* abc_box_id = 1 *)
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module MUXF7(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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(* abc_box_id = 2 *)
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module MUXF8(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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