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YosysHQ.yosys/techlibs/ice40
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Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
2020-05-19 01:42:40 +02:00
..
tests
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
2019-08-12 12:06:45 -07:00
.gitignore
…
abc9_model.v
ice40: specify fixes
2020-02-27 10:17:29 -08:00
arith_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
brams_init.py
…
brams_map.v
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 16:23:40 -08:00
brams.txt
ice40: match memory inference attribute values case insensitive.
2020-02-06 14:58:20 +00:00
cells_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cells_sim.v
xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells
2020-05-14 10:33:56 -07:00
dsp_map.v
Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
2019-08-08 12:56:05 -07:00
ff_map.v
ice40: split out cells_map.v into ff_map.v
2020-05-14 10:33:56 -07:00
ice40_braminit.cc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
ice40_ffinit.cc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
ice40_ffssr.cc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
ice40_opt.cc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
latches_map.v
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
Makefile.inc
ice40: split out cells_map.v into ff_map.v
2020-05-14 10:33:56 -07:00
synth_ice40.cc
xilinx/ice40/ecp5: zinit requires selected wires, so select them all
2020-05-14 10:33:56 -07:00