YRabbit c37db637c7 Gowin. Remove unnecessary modules ...

Primitives that are not planned for implementation for reasons of
belonging to old unsupported chips or representing composite complex IPs
rather than primitives are removed.
Also latches and large MUXes not planned for implementation.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

2025-03-28 06:34:26 +10:00

..

arith_map.v

gowin: Fix X output of $alu techmap

2023-05-01 17:56:41 +02:00

brams_map.v

gowin: Fix SDP write enable port.

2024-01-30 17:06:59 +10:00

brams.txt

gowin: Change BYTE ENABLE handling.

2024-01-27 17:19:49 +10:00

cells_map.v

iopadmap: Add native support for negative-polarity output enable.

2021-11-09 15:40:16 +01:00

cells_sim.v

Update ALU MULT mode in gowin to match nextpnr

2024-12-23 11:12:48 +01:00

cells_xtra_gw1n.v

Gowin. Remove unnecessary modules

2025-03-28 06:34:26 +10:00

cells_xtra_gw2a.v

Gowin. Remove unnecessary modules

2025-03-28 06:34:26 +10:00

cells_xtra_gw5a.v

Gowin. Remove unnecessary modules

2025-03-28 06:34:26 +10:00

cells_xtra.py

Gowin. Remove unnecessary modules

2025-03-28 06:34:26 +10:00

lutrams_map.v

gowin: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

lutrams.txt

gowin: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

Makefile.inc

gowin: split cells_xtra by family

2024-11-26 15:42:22 +01:00

synth_gowin.cc

gowin: split cells_xtra by family

2024-11-26 15:42:22 +01:00