Clifford Wolf 9923762461 Fixed "test_cell -simlib all"

2014-09-01 15:37:56 +02:00

..

cmos

Added test comments to techlibs/cmos/cmos_cells.lib

2014-01-29 10:51:02 +01:00

common

Fixed "test_cell -simlib all"

2014-09-01 15:37:56 +02:00

xilinx

Renamed $lut ports to follow A-Y naming scheme

2014-08-15 14:18:40 +02:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00