Charlotte 4e94f62116 simlib: blackbox $print cell ...

It's possible to `generate` the appropriate always blocks per the
triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter.

2023-08-11 04:46:52 +02:00

..

achronix

Test fixes for latest iverilog

2022-09-21 15:46:43 +02:00

anlogic

anlogic: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

common

simlib: blackbox $print cell

2023-08-11 04:46:52 +02:00

coolrunner2

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

easic

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

ecp5

ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model

2023-04-06 10:18:48 +01:00

efinix

efinix: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

fabulous

fabulous: Add support for LUT6s

2023-04-12 18:42:09 +02:00

gatemate

gatemate: Prevent implicit declaration of ram_{we,en}

2023-06-05 19:08:44 +02:00

gowin

Merge pull request #3737 from yrabbit/all-primitives-script

2023-05-09 11:13:51 +02:00

greenpak4

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

ice40

ice40: Fix path delay definitions

2023-03-10 10:48:05 +01:00

intel

Fitting help messages to 80 character width

2022-08-24 10:40:57 +12:00

intel_alm

intel_alm: re-enable 8x40-bit M10K support

2023-05-29 06:42:03 +01:00

machxo2

Add PLL and EBR related primitives

2023-04-10 12:39:09 +02:00

nexus

nexus: Fix BRAM write enable in PDP mode

2023-01-04 17:59:36 +01:00

quicklogic

Fitting help messages to 80 character width

2022-08-24 10:40:57 +12:00

sf2

Test fixes for latest iverilog

2022-09-21 15:46:43 +02:00

xilinx

Update Xilinx cell definitions, fixes #3699

2023-03-23 09:44:36 +01:00

.gitignore

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