YosysHQ.yosys

code_hdl_models_arbiter_tb.v

Some fixes in tests/asicworld/*_tb.v

2016-05-20 17:13:11 +02:00

code_hdl_models_arbiter.v

Fixed CRLF line endings

2015-08-13 09:35:00 +02:00

code_hdl_models_cam.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_clk_div_45.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_clk_div.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_d_ff_gates.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_d_latch_gates.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_decoder_2to4_gates.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_decoder_using_assign.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_decoder_using_case.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_dff_async_reset.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_dff_sync_reset.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_encoder_4to2_gates.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_encoder_using_case.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_encoder_using_if.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_full_adder_gates.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_full_subtracter_gates.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_gray_counter.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_GrayCounter.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_half_adder_gates.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_lfsr_updown.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_lfsr.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_mux_2to1_gates.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_mux_using_assign.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_mux_using_case.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_mux_using_if.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_one_hot_cnt.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_parallel_crc.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_parity_using_assign.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_parity_using_bitwise.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_parity_using_function.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_pri_encoder_using_assign.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_rom_using_case.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_serial_crc.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_tff_async_reset.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_tff_sync_reset.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_uart.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_up_counter_load.v

initial import

2013-01-05 11:13:26 +01:00

code_hdl_models_up_counter.v

Some ASCII encoding fixes (comments and docs) by Larry Doolittle

2015-08-13 09:30:20 +02:00

code_hdl_models_up_down_counter.v

initial import

2013-01-05 11:13:26 +01:00

code_specman_switch_fabric.v

initial import

2013-01-05 11:13:26 +01:00

code_tidbits_asyn_reset.v

initial import

2013-01-05 11:13:26 +01:00

code_tidbits_blocking.v

initial import

2013-01-05 11:13:26 +01:00

code_tidbits_fsm_using_always.v

initial import

2013-01-05 11:13:26 +01:00

code_tidbits_fsm_using_function.v

initial import

2013-01-05 11:13:26 +01:00

code_tidbits_fsm_using_single_always.v

initial import

2013-01-05 11:13:26 +01:00

code_tidbits_nonblocking.v

initial import

2013-01-05 11:13:26 +01:00

code_tidbits_reg_combo_example.v

initial import

2013-01-05 11:13:26 +01:00

code_tidbits_reg_seq_example.v

initial import

2013-01-05 11:13:26 +01:00

code_tidbits_syn_reset.v

initial import

2013-01-05 11:13:26 +01:00

code_tidbits_wire_example.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_addbit.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_always_example.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_bus_con.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_comment.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_counter_tb.v

Some fixes in tests/asicworld/*_tb.v

2016-05-20 17:13:11 +02:00

code_verilog_tutorial_counter.v

Fixed CRLF line endings

2015-08-13 09:35:00 +02:00

code_verilog_tutorial_d_ff.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_decoder_always.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_decoder.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_escape_id.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_explicit.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_first_counter_tb.v

Some fixes in tests/asicworld/*_tb.v

2016-05-20 17:13:11 +02:00

code_verilog_tutorial_first_counter.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_flip_flop.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_fsm_full_tb.v

Some fixes in tests/asicworld/*_tb.v

2016-05-20 17:13:11 +02:00

code_verilog_tutorial_fsm_full.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_good_code.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_if_else.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_multiply.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_mux_21.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_n_out_primitive.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_parallel_if.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_parity.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_simple_function.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_simple_if.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_task_global.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_tri_buf.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_v2k_reg.v

initial import

2013-01-05 11:13:26 +01:00

code_verilog_tutorial_which_clock.v

initial import

2013-01-05 11:13:26 +01:00

generate_mk.py

Convert autotest script wrapper

2026-04-16 11:00:44 +02:00

README

Another block of spelling fixes

2015-08-14 23:27:05 +02:00

xfirrtl

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00