Krystine Sherwin 9dcffc3dbf analogdevices: Adding RBRAM2 and -tech

2026-03-05 05:37:12 +00:00

..

abc9_model.v

Create synth_analogdevices

2026-03-05 05:37:12 +00:00

arith_map.v

analogdevices: update timing model

2026-03-05 05:37:12 +00:00

brams_defs.vh

Create synth_analogdevices

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brams_map.v

analogdevices: Adding RBRAM2 and -tech

2026-03-05 05:37:12 +00:00

brams.txt

analogdevices: Adding RBRAM2 and -tech

2026-03-05 05:37:12 +00:00

cells_map.v

Create synth_analogdevices

2026-03-05 05:37:12 +00:00

cells_sim.v

analogdevices: Adding RBRAM2 and -tech

2026-03-05 05:37:12 +00:00

cells_xtra.py

Create synth_analogdevices

2026-03-05 05:37:12 +00:00

cells_xtra.v

analogdevices: remove some extra cells!

2026-03-05 05:37:12 +00:00

dsp_map.v

Create synth_analogdevices

2026-03-05 05:37:12 +00:00

ff_map.v

test suite

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lut_map.v

analogdevices: update timing model

2026-03-05 05:37:12 +00:00

lutrams_map.v

analogdevices: Native LUTRAM primitives

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lutrams.txt

analogdevices: Native LUTRAM primitives

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Makefile.inc

Create synth_analogdevices

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mux_map.v

Create synth_analogdevices

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retarget_map.v

analogdevices: user retargeting

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synth_analogdevices.cc

analogdevices: Adding RBRAM2 and -tech

2026-03-05 05:37:12 +00:00