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YosysHQ.yosys/techlibs/ecp5
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Eddie Hung 71906fab51 Nitpick cleanup for ecp5
2019-12-27 16:57:08 -08:00
..
tests
…
.gitignore
ecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 13:46:36 +01:00
abc9_5g_nowide.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_5g.box
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_5g.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_map.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_model.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_unmap.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
arith_map.v
…
bram.txt
ecp5: Fix shuffle_enable port
2019-10-01 14:14:46 +01:00
brams_connect.py
ecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 13:46:36 +01:00
brams_init.py
…
brams_map.v
ecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 13:46:36 +01:00
cells_bb.v
ecp5: Add ECLKBRIDGECS blackbox
2019-10-11 14:50:33 +01:00
cells_ff.vh
Fix bitwidth mismatch; suppresses iverilog warning
2019-12-11 13:02:07 -08:00
cells_io.vh
…
cells_map.v
ecp5: Add support for mapping PRLD FFs
2019-12-07 13:04:36 +00:00
cells_sim.v
Nitpick cleanup for ecp5
2019-12-27 16:57:08 -08:00
dsp_map.v
…
ecp5_ffinit.cc
…
ecp5_gsr.cc
ecp5_gsr: Fix typo
2019-08-31 09:58:46 +01:00
latches_map.v
…
lutram.txt
…
lutrams_map.v
…
Makefile.inc
Makefile: don't assume python is called python3
2019-10-19 14:04:52 +08:00
synth_ecp5.cc
Nitpick cleanup for ecp5
2019-12-27 16:57:08 -08:00