Jannis Harder 6a0ee6e4fb Revert sim's cycle_width default back to 10, but keep -width option

2025-10-20 14:40:05 +02:00

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tb

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.gitignore

Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.

2025-07-22 10:38:38 +00:00

adff.v

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adffe.v

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adlatch.v

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aldff.v

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aldffe.v

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assume_x_first_step.ys

Assume x values for missing signal data in FST

2024-10-02 12:08:48 +02:00

dff.v

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dffe.v

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dffsr.v

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dlatch.v

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dlatchsr.v

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run-test.sh

test: restore verific handling, nicer naming

2024-12-13 10:24:47 +01:00

sdff.v

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sdffce.v

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sdffe.v

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sim_adff.ys

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sim_adffe.ys

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sim_adlatch.ys

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sim_aldff.ys

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sim_aldffe.ys

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sim_cycles.ys

Revert sim's cycle_width default back to 10, but keep -width option

2025-10-20 14:40:05 +02:00

sim_dff.ys

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sim_dffe.ys

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sim_dffsr.ys

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sim_dlatch.ys

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sim_dlatchsr.ys

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sim_sdff.ys

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sim_sdffce.ys

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sim_sdffe.ys

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simple_assign.v

Assume x values for missing signal data in FST

2024-10-02 12:08:48 +02:00

simple_assign.vcd

Assume x values for missing signal data in FST

2024-10-02 12:08:48 +02:00

var_reference_with_whitespace.vcd

Fix: handle VCD variable references with and without whitespace

2024-10-01 11:51:20 +02:00

var_reference_without_whitespace.vcd

Fix: handle VCD variable references with and without whitespace

2024-10-01 11:51:20 +02:00

vcd_var_reference_whitespace.ys

Fix: handle VCD variable references with and without whitespace

2024-10-01 11:51:20 +02:00

vector_assign.il

Fix: handle VCD variable references with and without whitespace

2024-10-01 11:51:20 +02:00