Claire Wolf 590d8eccb7

Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix ...

techmap: Fix cell names with _TECHMAP_REPLACE_.*

2020-03-26 19:03:37 +01:00

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aiger

tests/aiger: Add missing .gitignore

2020-02-15 19:52:21 +01:00

arch

fix argument order for macOS compatibility

2020-03-18 15:11:49 +01:00

asicworld

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bram

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errors

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fsm

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hana

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liberty

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lut

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memfile

Added 'set -e' into tests/memfile/run-test.sh

2020-02-06 10:45:40 -03:00

memories

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opt

Merge pull request #1576 from YosysHQ/eddie/opt_merge_init

2020-02-05 14:56:26 -08:00

opt_share

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proc

proc_clean: fix order of switch insertion.

2019-08-19 16:44:23 +00:00

realmath

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rpc

rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors

2020-03-06 15:29:01 +01:00

sat

Merge pull request #1638 from YosysHQ/eddie/fix1631

2020-02-05 19:31:18 +01:00

select

Do not warn on empty selection with prefixed arg_memb.

2020-03-23 17:50:11 +00:00

share

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simple

Fix partsel expr bit width handling and add test case

2020-03-08 16:12:12 +01:00

simple_abc9

Update simple_abc9 tests

2020-02-27 10:17:29 -08:00

smv

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sva

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svinterfaces

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svtypes

Revert typedef tests to standard grammar.

2020-03-22 18:20:46 -07:00

techmap

techmap: Fix cell names with _TECHMAP_REPLACE_.*

2020-03-23 11:17:07 +01:00

tools

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unit

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various

Add test for abc9+mince issue

2020-03-20 20:35:28 +00:00

vloghtb

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