Marcelina Kościelnicka a1a0abf52a equiv_induct: Fix up assumption for $equiv cells in -undef mode. ...

Before this fix, equiv_induct only assumed that one of the following is
true:

- defined value of A is equal to defined value of B
- A is undefined

This lets through valuations where A is defined, B is undefined, and
the defined (meaningless) value of B happens to match the defined value
of A.  Instead, tighten this up to OR of the following:

- defined value of A is equal to defined value of B, and B is not
  undefined
- A is undefined

2020-07-27 18:36:13 +02:00

..

aiger

tests: aiger test for wire->start_offset != 0

2020-05-02 10:00:32 -07:00

arch

satgen: Add support for dffe, sdff, sdffe, sdffce cells.

2020-07-24 03:19:21 +02:00

asicworld

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00

bram

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errors

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fsm

tests: fsm to use a randomly-generated seed

2020-04-24 14:31:33 -07:00

hana

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liberty

dfflibmap: Refactor to use dfflegalize internally.

2020-07-09 18:51:03 +02:00

lut

Forgot to commit

2019-07-16 12:44:26 -07:00

memfile

Added 'set -e' into tests/memfile/run-test.sh

2020-02-06 10:45:40 -03:00

memories

memory_dff: Fix checking of feedback mux input when more than one mux

2019-07-02 13:35:50 +01:00

opt

clk2fflogic: Support all FF types.

2020-07-24 03:19:48 +02:00

opt_share

Support various binary operators in opt_share

2019-08-04 19:06:38 +02:00

proc

proc_clean: fix order of switch insertion.

2019-08-19 16:44:23 +00:00

realmath

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rpc

rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors

2020-03-06 15:29:01 +01:00

sat

satgen: Add support for dffe, sdff, sdffe, sdffce cells.

2020-07-24 03:19:21 +02:00

select

Merge pull request #1949 from YosysHQ/eddie/select_blackbox

2020-04-22 15:35:05 -07:00

share

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simple

Expand tests/simple/constmuldivmod.v

2020-05-28 22:59:04 +02:00

simple_abc9

abc9: test to use box file instead of auto

2020-05-14 10:33:56 -07:00

smv

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sva

Fix "verific -extnets" for more complex situations

2019-03-26 14:17:46 +01:00

svinterfaces

Fix typo in tests/svinterfaces/runone.sh

2019-05-03 14:40:51 +02:00

svtypes

static cast: add tests

2020-06-19 17:40:38 -07:00

techmap

zinit: Refactor to use FfInitVals.

2020-07-24 11:22:31 +02:00

tools

autotest.sh to define _AUTOTB when test_autotb

2019-06-28 14:56:22 -07:00

unit

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various

equiv_induct: Fix up assumption for $equiv cells in -undef mode.

2020-07-27 18:36:13 +02:00

verilog

Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings

2020-06-03 08:37:07 -07:00

vloghtb

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