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a330c6836318d43d52cda68959f2b86c2b2ede9c
YosysHQ.yosys
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frontends
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ast
History
Clifford Wolf
a330c68363
Fix handling of task output ports in clocked always blocks,
fixes
#857
...
Signed-off-by: Clifford Wolf <
clifford@clifford.at
>
2019-03-07 22:44:37 -08:00
..
ast.cc
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
ast.h
Only run derive on blackbox modules when ports have dynamic size
2019-03-02 12:36:46 -08:00
dpicall.cc
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
genrtlil.cc
Fix error for wire decl in always block,
fixes
#763
2019-03-02 11:56:44 -08:00
Makefile.inc
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
simplify.cc
Fix handling of task output ports in clocked always blocks,
fixes
#857
2019-03-07 22:44:37 -08:00
