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a4fd3cde8cb93f43f5fa0082cf244eb280a2581c
YosysHQ.yosys
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tests
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Clifford Wolf
56432a920f
Added defparam support to Verilog/AST frontend
2013-07-04 14:12:33 +02:00
..
asicworld
Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
2013-05-24 15:15:59 +02:00
hana
added more .gitignore files (make test)
2013-01-05 11:35:52 +01:00
i2c_bench
initial import
2013-01-05 11:13:26 +01:00
k68_vltor
Now only use value from "initial" when no matching "always" block is found
2013-03-31 11:51:12 +02:00
no-icarus
initial import
2013-01-05 11:13:26 +01:00
simple
Added defparam support to Verilog/AST frontend
2013-07-04 14:12:33 +02:00
tools
Improved vcdcd.pl (added -d option)
2013-05-14 09:41:47 +02:00
xsthammer
Added Altera Quartus support to xsthammer
2013-07-03 20:40:54 +02:00