Marcin Kościelnicki 2abe38e73e

iopadmap: Refactor and fix tristate buffer mapping. (#1527) ...

The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).

2019-12-04 08:44:08 +01:00

..

.gitignore

tests/techmap/run-test.sh to cope with *.ys

2019-08-23 11:09:50 -07:00

aigmap.ys

Add quick test

2019-09-30 15:34:04 -07:00

autopurge.ys

Hell let's add the original #1381 testcase too

2019-09-20 17:58:51 -07:00

clkbufmap.ys

clkbufmap: Add support for inverters in clock path.

2019-11-25 20:40:39 +01:00

dff2dffs.ys

Add -match-init option to dff2dffs.

2019-09-11 19:38:20 +02:00

extractinv.ys

Added extractinv pass

2019-09-19 04:02:48 +02:00

iopadmap.ys

iopadmap: Refactor and fix tristate buffer mapping. (#1527)

2019-12-04 08:44:08 +01:00

mem_simple_4x1_cells.v

Added tests/techmap/mem_simple_4x1

2014-02-21 12:06:40 +01:00

mem_simple_4x1_map.v

Added read-enable to memory model

2015-09-25 12:23:11 +02:00

mem_simple_4x1_runtest.sh

Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh

2014-03-11 11:59:58 +01:00

mem_simple_4x1_tb.v

Added tests/techmap/mem_simple_4x1

2014-02-21 12:06:40 +01:00

mem_simple_4x1_uut.v

Added tests/techmap/mem_simple_4x1

2014-02-21 12:06:40 +01:00

recursive_map.v

Add test

2019-08-20 20:05:16 -07:00

recursive_runtest.sh

Add test

2019-08-20 20:05:16 -07:00

recursive.v

Add test

2019-08-20 20:05:16 -07:00

run-test.sh

tests/techmap/run-test.sh to cope with *.ys

2019-08-23 11:09:50 -07:00

techmap_replace.ys

Extend test with renaming cells with prefix too

2019-10-02 12:43:18 -07:00

wireinit.ys

Fix _TECHMAP_REMOVEINIT_ handling.

2019-09-27 18:34:12 +02:00