12 lines
172 B
Verilog
12 lines
172 B
Verilog
module test(in, out);
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input in;
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output out;
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parameter p1 = 10;
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parameter p2 = 5;
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assign out = +p1;
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assign out = -p2;
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assign out = p1 + p2;
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assign out = p1 - p2;
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endmodule
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