15 lines
276 B
Verilog
15 lines
276 B
Verilog
module test (input [1:0] in, input enable, output reg out);
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always @(in or enable)
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if(!enable)
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out = 4'b0000;
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else begin
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case (in)
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2'b00 : out = 0 ;
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2'b01 : out = 1;
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2'b10 : out = 0;
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2'b11 : out = 1;
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endcase
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end
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endmodule
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