github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-17 13:26:56 +00:00
Code Issues Releases Wiki Activity
Files
a582b9d1849a9cb1f13323d8894de3fdb0bc6c90
YosysHQ.yosys/tests/i2c_bench/timescale.v
Clifford Wolf 7764d0ba1d initial import
2013-01-05 11:13:26 +01:00

3 lines
23 B
Verilog
Raw Blame History

`timescale 1ns / 10ps
Reference in New Issue View Git Blame Copy Permalink