Clifford Wolf 34e54cda5b Small improvement in SAT log messages

2014-03-13 13:12:49 +01:00

..

abc

- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().

2014-03-12 23:17:14 +01:00

cmds

- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().

2014-03-12 23:17:14 +01:00

fsm

Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys

2014-03-11 14:24:24 +01:00

hierarchy

Implemented read_verilog -defer

2014-02-13 13:59:13 +01:00

memory

Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect

2014-02-08 19:13:19 +01:00

opt

Fixed undef handling in opt_reduce

2014-03-06 14:18:34 +01:00

proc

Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst

2014-02-21 23:34:45 +01:00

sat

Small improvement in SAT log messages

2014-03-13 13:12:49 +01:00

techmap

Merged OSX fixes from Siesh1oo with some modifications

2014-03-13 12:48:10 +01:00