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a6aeee4e1a41aa71d08ebac48686001ec050f973
YosysHQ.yosys
/
frontends
/
verilog
History
Eddie Hung
760096e8d2
Merge pull request
#1703
from YosysHQ/eddie/specify_improve
...
Improve specify parser
2020-02-21 09:15:17 -08:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Fix handling of z_digit "?" and fix optimization of cmp with "z"
2019-09-13 13:39:39 +02:00
Makefile.inc
Read bigger Verilog files.
2019-05-18 14:20:30 +03:00
preproc.cc
Fixed some missing "verilog_" in documentation
2019-12-13 10:17:05 -03:00
verilog_frontend.cc
Add "verilog_defines -list" and "verilog_defines -reset"
2019-10-21 13:35:56 +02:00
verilog_frontend.h
Add specify parser
2019-04-23 21:36:59 +02:00
verilog_lexer.l
verilog: ignore '&&&' when not in -specify mode
2020-02-13 13:06:13 -08:00
verilog_parser.y
Merge pull request
#1703
from YosysHQ/eddie/specify_improve
2020-02-21 09:15:17 -08:00
