Clifford Wolf a7c6b37abf Added "kernel/yosys.h" and "kernel/yosys.cc"

2014-07-30 14:10:15 +02:00

..

bitpattern.h

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

calc.cc

Added $shift and $shiftx cell types (needed for correct part select behavior)

2014-07-29 16:35:13 +02:00

celltypes.h

Added $shift and $shiftx cell types (needed for correct part select behavior)

2014-07-29 16:35:13 +02:00

compatibility.cc

Merged OSX fixes from Siesh1oo with some modifications

2014-03-13 12:48:10 +01:00

compatibility.h

Hotfix for kernel/compatibility.h

2014-03-13 12:55:15 +01:00

consteval.h

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

driver.cc

Added "kernel/yosys.h" and "kernel/yosys.cc"

2014-07-30 14:10:15 +02:00

log.cc

Added "kernel/yosys.h" and "kernel/yosys.cc"

2014-07-30 14:10:15 +02:00

log.h

Added "kernel/yosys.h" and "kernel/yosys.cc"

2014-07-30 14:10:15 +02:00

modwalker.h

Refactoring: Renamed RTLIL::Module::cells to cells_

2014-07-27 01:51:45 +02:00

register.cc

Renamed "write_autotest" to "test_autotb" and moved to passes/tests/

2014-07-29 21:12:50 +02:00

register.h

Added "kernel/yosys.h" and "kernel/yosys.cc"

2014-07-30 14:10:15 +02:00

rtlil.cc

Added "techmap -map %{design-name}"

2014-07-29 16:35:13 +02:00

rtlil.h

Added "kernel/yosys.h" and "kernel/yosys.cc"

2014-07-30 14:10:15 +02:00

satgen.h

Added $shift and $shiftx cell types (needed for correct part select behavior)

2014-07-29 16:35:13 +02:00

sigtools.h

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

toposort.h

Added topological sorting to techmap

2014-07-27 16:43:39 +02:00

yosys.cc

Added "kernel/yosys.h" and "kernel/yosys.cc"

2014-07-30 14:10:15 +02:00

yosys.h

Added "kernel/yosys.h" and "kernel/yosys.cc"

2014-07-30 14:10:15 +02:00